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JOURNAL PUBLICATIONS

  • Hayun Chung, Minji Hyun, Jungwon Kim, "A 360-fs-Time-Resolution 7-bit Stochastic Time-to-Digital Converter With Linearity Calibration Using Dual Time Offset Arbiters in 65-nm CMOS," IEEE Journal of Solid-State Circuits, vol. 56, no. 3, pp. 940-949, 2021.

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  • Minji Hyun, Changmin Ahn, Yongjin Na, Hayun Chung, and Jungwon Kim, "Attosecond electronic timing with rising edges of photocurrent pulses," Nature Communications, vol. 11, article 3667, 2020.

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  • Hayun Chung, "Non-linear MLE-based digital equalizer for ADC-based backplane receivers," Electronics Letters, vol. 52, no. 13, pp. 1106-1108, 2016.

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  • Hayun Chung, "ADC-based backplane receivers: motivations, issues and future," Journal of Semiconductor Technology and Science, vol. 16, no. 3, pp. 300-311, 2016.

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  • Hayun Chung, Zeynep Toprak Deniz, Alexander Rylyakov, John Bulzacchelli, Daniel Friedman and Gu-Yeon Wei, "A 7.5 GS/s flash ADC and a 10.24 GS/s time-interleaved ADC for backplane receivers in 65 nm CMOS," Analog Integrated Circuits and Signal Processing, vol. 85, no. 2, pp. 299-310, 2015.

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  • Hayun Chung and Gu-Yeon Wei, “ADC-Based Backplane Receiver Design-Space Exploration,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 7, pp.1539 - 1547, 2014.

 

  • Hayun Chung, Andrzej Radecki, Noriyuki Miura, Hiroki Ishikuro and Tadahiro Kuroda, “A 0.025-0.45 W 60%-Efficiency Inductive-Coupling Power Transceiver with 5-bit Dual-Frequency Feedforward Control for Non-Contact Memory Cards,” IEEE Journal of Solid-State Circuits, vol. 47, no. 10, pp.2496-2504, 2012.

 

  • Hayun Chung, Hiroki Ishikuro and Tadahiro Kuroda, “A 10-bit 80-MS/s Decision-Select Successive Approximation TDC in 65-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 47, no. 5, pp.1232-1241, 2012.

 

  • Andrzej Radecki, Hayun Chung, Yoichi Yoshida, Noriyuki Miura, Tsunaaki Shidei, Hiroki Ishikuro and Tadahiro Kuroda, “6W/25mm2 Wireless Power Transmission for Non-Contact Wafer-Level Testing,” IEICE Transactions on Electronics, vol. E95-C, no. 4, pp.668-676, 2012.

 

  • Hayun Chung and Gu-Yeon Wei, “Simulated-annealing-based adaptive equaliser for on-die variation compensation”, Electronics Letters, vol. 48, no. 1, pp. 18-19, 2012.

 

  • Hayun Chung, Deog-Kyoon Jeong and Wonchan Kim, “A 128-phase PLL using interpolation technique,” (Invited) Journal of Semiconductor Technology and Science,, vol. 3, no. 4, pp. 181-187, 2003.

PATENTS

  • Hayun Chung, "Stochastic time-to-digital converter and operating method thereof," US Patent 10,840,928, issued November 17, 2020.

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  • Jungwon Kim, Hayun Chung, Minji Hyun, Yongjin Na, "System for generating low-jitter digital clock signals using pulsed laser," US Patent Application 16/801432, filed February 26, 2020.

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  • Hayun Chung and Jungwon Kim, "Semiconductor device and clock system including pulse laser-based clock distribution network," US Patent Application 16/688599, filed November 19, 2019.

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  • Hayun Chung, "Stochastic time-to-digital converter and operating method thereof," EU Patent Application 19209126.2, filed November 14, 2019.

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  • Hayun Chung, "High-speed and low-power pipelined ADC using dynamic reference voltage and 2-stage sample-and-hold," US Patent 10,411,722, issued September 10, 2019.

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  • Hayun Chung, "Digital equalizer and digital equalizing method," US Patent 9,998,302, issued June 12, 2018.

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  • Hayun Chung, "확률기반 시간-디지털 변환기 및 그것의 동작 방법," 대한민국 특허 10-2156696, 2020년 9월 10일 등록. 

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  • Hayun Chung and Jungwon Kim, "펄스 레이저 기반의 클럭 분산 네트워크를 포함하는 반도체 장치 및 클럭 시스템," 대한민국 특허 10-2161837, 2020년 9월 24일 등록.

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  • Jungwon Kim, Hayun Chung, Minji Hyun, Yongjin Na, "펄스 레이저를 이용한 저-지터 디지털 클럭 신호 생성 시스템, 그리고 마이크로파 생성 시스템," 대한민국 특허 10-2087192, 2020년 3월 4일 등록. 

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  • Hayun Chung, "다이나믹 레퍼런스 및 2단 샘플앤드홀드를 이용한 고속, 저전력 파이프라인드 아날로그-디지털 변환기," 대한민국 특허 10-1986938, 2019년 6월 등록.

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CONFERENCE PROCEEDINGS

  • Yasuyuki Hiraku, Isamu Hayashi, Hayun Chung, Tadahiro Kuroda and Hiroki Ishikuro, “A 0.5V 10MHz-to-100MHz 0.47μW/MHz Power Scalable AD-PLL in 40nm CMOS,” IEEE A-SSCC, Nov. 2012.

 

  • Yasuhiro Take, Hayun Chung, Noriyuki Miura and Tadahiro Kuroda, “Simultaneous Data and Power Transmission using Nested Clover Coils,” ASP-DAC, Feb. 2012.

 

  • Hayun Chung and Tadahiro Kuroda, “Inductive-Coupling Interfaces for High-Speed Low-Power Proximity Communications”, (Invited) IEEE MWSCAS, Aug. 2011.

 

  • Hayun Chung and Gu-Yeon Wei, “Design Considerations for ADC-Based Backplane Receivers”, (Invited) IEEE MWSCAS, Aug. 2011.

 

  • Andrzej Radecki, Hayun Chung, Yoichi Yoshida, Noriyuki Miura, Tsunaaki Shidei, Hiroki Ishikuro and Tadahiro Kuroda, “6W/25mm2 Inductive Power Transfer for Non-Contact Wafer-Level Testing,” IEEE ISSCC, Feb. 2011.

 

  • Hayun Chung and Gu-Yeon Wei, “Design-Space Exploration of Backplane Receivers with High-Speed ADCs and Digital Equalization,” IEEE CICC, Sep. 2009.

 

  • Hayun Chung, Alexander Rylyakov, Zeynep Toprak Deniz, John Bulzacchelli, Gu-Yeon Wei and Daniel Friedman, “A 7.5-GS/s 3.8-ENOB 52-mW flash ADC with clock duty cycle control in 65nm CMOS,” Symposium on VLSI Circuits, Jun. 2009.

 

  • Hayun Chung, Andrew Liu and Gu-Yeon Wei, “A 12.5-Gbps, 7-bit transmit DAC with 4-tap LUT-based equalization in 0.13μm CMOS,” IEEE CICC, Sep. 2008.

 

  • Hayun Chung, Deog-kyoon Jeong and Wonchan Kim, “A 128-phase PLL using interpolation technique,” SOC Design Conference, Nov. 2003.

 

  • Dongwon Yang, Heesoo Song, Hayun Chung, Deog-Kyoon Jeong and Wonchan Kim, “A 0.13μm CMOS Parallel Link Transceiver for 10Gbps Data Transmission,” Korean Conference on Semiconductor, Feb. 2003.

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